DVD - Lecture 2: Verilog
1:16:27
DVD - Lecture 3: Logic Synthesis - Part 1
34:52
How to write Synthesizeable RTL
32:07
IC Design & Manufacturing Process : Beginners Overview to VLSI
29:29
DVD - Lecture 2b: Verilog Syntax
1:20:22
DVD - Lecture 4: Logic Synthesis - Part II
1:05:09
DVD - Lecture 6: Moving to the Physical Domain
30:23
Intro to Verilog and ModelSim, Part1
56:13