AXI Stream basics for beginners! A Stream FIFO example in Verilog.
17:40
AXI Introduction Part 1: How AXI works and AXI-Lite transaction example
17:47
What is a FIFO in an FPGA
11:58
10 tips for writing a clear state machine in Verilog: A UART transmitter example.
18:56
The AXI Protocol, AXI MM and AXI Streaming Interfaces [English]
15:11
How the AXI-style ready/valid handshake works
20:00
Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)
16:07
ZYNQ Training - session 03 - axi stream interface
27:49