Digital Design & Comp. Arch. - Lecture 7b: HW Description Lang. & Verilog (ETH Zürich, Spring 2020)
1:31:24
Digital Design & Computer Architecture - Lecture 8: Timing & Verification (ETH Zürich, Spring 2020)
1:05:14
Digital Design & Computer Architecture - Lecture 16b: Branch Prediction I (ETH Zürich, Spring 2020)
1:45:45
Digital Design and Comp. Arch. - Lecture 2: Tradeoffs, Metrics, Mysteries in Comp Arch (Spring 2022)
1:29:48
Digital Design & Comp. Arch. - Lecture 9: Von Neumann Model ISA LC3 MIPS (ETH Zürich, Spring 2020)
1:32:43
Digital Design & Comp. Arch. - Lecture 15b: OoO, DataFlow & LD/ST Handling (ETH Zürich, Spring 2020)
1:34:20
Digital Design & Computer Arch. - Lecture 21b: Memory Hierarchy and Caches (ETH Zürich, Spring 2020)
1:28:22
Digital Design & Computer Architecture - Lecture 13: Pipelining (ETH Zürich, Spring 2020)
1:33:23