Layout Basics
23:18
Cadence Virtuoso:: Layout of NAND Gate || Part-2.
21:13
Layout DRC, LVS, PEX and Post Layout Simulation
19:41
Cadence Virtuoso:: CMOS Inverter Layout || Part-2.
52:26
Place and Route in Cadence Innovus | full PnR flow | Cadence Innovus demo I Innovus Tutorial
29:46
Testbench and analysis
58:12
vlsi教學影片(layout)
55:23
FinFET Technologies for Analog Design
33:25