Cadence IC6.1.6/6.1.7 Virtuoso Tutorial -1 Part 5 (Post-layout Simulation and tape out )
32:44
Cadence IC6.1.6/6.1.7 Virtuoso Tutorial -1 Part 4 (Layout Design and Physical Verification)
31:21
Design a CMOS inverter using Cadence Virtuoso
44:06
Layout design and post layout simulation in Spectre
30:27
cshrc, bashrc creation or modification for VLSI tools
33:43
Cadence IC6.16/6.17 Virtuoso Tutorial -1 Part 2 (Simulation, Analysis and calculator use)
21:13
Layout DRC, LVS, PEX and Post Layout Simulation
37:47
Cadence IC6.1.6/6.1.7 Virtuoso Tutorial -1 Part1 (Schematic and symbol Design)
7:24