10 tips for writing a clear state machine in Verilog: A UART transmitter example.
10:15
Vivado IP generator tricks: Generating IP, saving to version control, and generating example code!
29:28
My favourite state machine, always blocks: one or many? and simplifying your SystemVerilog Style!
20:12
Tips for Verilog beginners from a Professional FPGA Engineer
20:34
Example Interview Questions for a job in FPGA, VHDL, Verilog
12:11
AXI Stream basics for beginners! A Stream FIFO example in Verilog.
29:23
The Critical FPGA Basics: Always blocks, Inferred latches, and why the FPGA needs a clock, anyway?!
55:27
Verilog, FPGA, Serial Com: Overview + Example
20:24