The Critical FPGA Basics: Always blocks, Inferred latches, and why the FPGA needs a clock, anyway?!
29:28
My favourite state machine, always blocks: one or many? and simplifying your SystemVerilog Style!
23:04
AXI-Stream Arbiter example
31:18
EEVblog 1662 - Vintage Tandy 200 Portable Computer Claytons Repair/Teardown
20:00
Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)
20:12
Tips for Verilog beginners from a Professional FPGA Engineer
11:50
Are FPGA Engineers in Demand? | Exploring 10 Common Applications of FPGAs
20:34
Example Interview Questions for a job in FPGA, VHDL, Verilog
18:08