RISC-V Single Cycle Processor: RTL Design, Integration, and Testing (In Arabic)
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Video 3: Realization of Multiplier using structural modelling
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"🚀 4-Bit Register Design in Verilog | Step-by-Step Guide with Xilinx Vivado 🔧📘"
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Smart home project software "The code" ( جزء 2 من مشروع مادة الكنترول )
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شرح تقرير البرمجة لطلاب المرحلة الثانية شعبة A | Matlab2
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design a 4 bit adder program using verilog hdl and implement it using basys 3
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VHDL LAB #6 #2024
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Discrete Math ch11 | Tree Presentation | DSP TEAM | Arabic
15:07