DVD - Lecture 6d: Hierarchical Design
19:50
DVD - Lecture 6e: Power Planning
12:28
DVD - Lecture 7e: Placement in Practice
8:26
DVD - Lecture 8g: Clock Domain Crossing (CDC)
11:38
DVD - Lecture 9b: Maze Routing
1:40:35
VLSI System Verilog : A Beginner's Guide to Hardware Description Language
10:56
DVD - Lecture 8d: Clock Tree Synthesis in EDA Tools
7:00
DVD - Lecture 7a: Standard Cell Placement
9:41