DVD - Lecture 11: Sign Off and Chip Finishing - Part 1
29:43
DVD Lecture 11: Sign Off and Chip Finishing - Part 2
56:15
DVD - Lecture 9: Routing
18:08
VLSI Physical Design: Powerplan
53:56
DVD - Lecture 10: Packaging and I/O Circuits
13:55
Double Patterning to the rescue (LELE, LFLE, SADP) - Part 1
1:05:09
DVD - Lecture 6: Moving to the Physical Domain
31:37
WEBINAR: Design Timing Closure Considering Process Variations
20:51