PD Lec 17- Floorplanning & IO Placement [part-3] | VLSI | Physical Design
![](https://i.ytimg.com/vi/AW6OwZxY7VY/mqdefault.jpg)
14:21
PD Lec 18- Macro Placement & Floor-planning [part-4] | VLSI | Physical Design
![](https://i.ytimg.com/vi/KnUliEaCxvk/mqdefault.jpg)
1:15:09
PNR placement discussion on placement blockages & congestion
![](https://i.ytimg.com/vi/IG0EWRcDkl8/mqdefault.jpg)
7:59
PD Lec 19- Macro Placement Guidelines & Floor-planning [part-5] | VLSI | Physical Design
![](https://i.ytimg.com/vi/X6e3Yshs0Ys/mqdefault.jpg)
18:08
VLSI Physical Design: Powerplan
![](https://i.ytimg.com/vi/Lg0mZPUJQ9M/mqdefault.jpg)
13:55
PD Lec 11 - Constraints File | PD Inputs part-4 | VLSI | Physical Design
![](https://i.ytimg.com/vi/8WdYWx48ac8/mqdefault.jpg)
21:46
The ULTIMATE VLSI ROADMAP | How to get into semiconductor industry? | Projects | Free Resources📚
![](https://i.ytimg.com/vi/Z1Cxbn5LOYg/mqdefault.jpg)
7:21
PD Lec 15- Floor-planning [part-1] | VLSI | Physical Design
![](https://i.ytimg.com/vi/VcxRj-Q_R9I/mqdefault.jpg)
10:49