Logic Equivalence Check | Synopsys Formality Tutorial | RTL-to-GDSII flow | LEC Check
11:46
Physical Design Flow | PnR flow | RTL-to-GDSII flow | Back End Flow | Innovus tool flow
52:26
Place and Route in Cadence Innovus | full PnR flow | Cadence Innovus demo I Innovus Tutorial
21:00
Understanding Logic Equivalence Check in VLSI | What is LEC?
11:16
Logic Synthesis of RTL | Synopsys Design Compiler | Synopsys DC | dc_shell | DC Tutorial
21:25
RTL Design & Simulation | Synopsys VCS Tutorial | Functional verification of RTL
26:44
IO pad placement | .io file writing | pad placement in Physical design flow
1:15:09
PNR placement discussion on placement blockages & congestion
7:51