Introduction to Cadence Virtuoso: VLSI Systems Lab Series 2
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Getting Started with Xilinx Vivado & Nexys A7 FPGA: VLSI System Lab Series 1
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How to extract layout using virtuoso XL (2 input NAND gate example): VLSI Systems Lab Series 4
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Creating the Layout of an Inverter using Cadence Virtuoso: VLSI Systems Lab Series 3b
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Performing DRC, LVS and Post-Layout Simulations using Cadence Virtuoso: VLSI Systems Lab Series 3c
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Introduction to Hierarchical Design using Virtuoso: 2 input AND gate example
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Calculate Cgs by Cadence Simulation || Gate Capacitance of MOS - Cadence Virtuoso #10
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Understanding CMOS Logic: The Heart of VLSI Systems
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