32:18

Interconnect Modeling (Part 2)

28:38

Design Rule Check

36:11

Techniques to Reduce Power

34:17

Fault Modeling (Part 1)

28:50

Physical Synthesis (Part 1)

34:22

Placement (Part 1)

40:36

MOS Parasitics and SPICE Model

33:04

CLOCK NETWORK SYNTHESIS (PART 1)