21:33

Key Concepts of the Easier UVM Code Generator

25:22

Easier UVM - Transaction Classes

27:54

Easier UVM - Register Layer

1:37:43

Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification

1:04:29

Don't Be Afraid of UVM (UVM for Hardware Designers)

52:00

Webinar | Introduction to the UVM Register Layer

25:36

TLM Connections in UVM

26:46

Easier UVM - Sequences