4.6 - Linear Delay model
![](https://i.ytimg.com/vi/tJ41dqons9w/mqdefault.jpg)
33:25
4.7 - Logical effort and Parasitic delay
![](https://i.ytimg.com/vi/znuxpaxhUu4/mqdefault.jpg)
21:25
CombCkt - 3 - Gate Sizing
![](https://i.ytimg.com/vi/PfFGF0vKC1M/mqdefault.jpg)
25:34
CombCkt - 5 - Gate Delay
![](https://i.ytimg.com/vi/BIXuGEzHJsM/mqdefault.jpg)
31:56
Inverter - 13 - Elmore Delay Model
![](https://i.ytimg.com/vi/NdBG4gOeLvc/mqdefault.jpg)
5:06
IC Design I | Elmore Delay is SUPER EASY!
![](https://i.ytimg.com/vi/_KJM43nHO-o/mqdefault.jpg)
11:24
Effort Delay, Logical Effort, Electrical Effort, Parasitic Delay | Know - How
![](https://i.ytimg.com/vi/FYwNeSv8pv4/mqdefault.jpg)
18:18
4.3 - Delay of FO4 inverter
![](https://i.ytimg.com/vi/clti1dBVVf0/mqdefault.jpg)
18:37