8:25

#26 if-else in verilog |conditional statement in verilog |Hardware implementation of if-else verilog

25:58

#24 INITIAL block in verilog | use of INITIAL procedural block in verilog

10:16

Verilog Blocking and Non Blocking statements | Blocking Vs Non Blocking | VLSI Interview Question

18:35

Event Regions in Verilog and Race Condition

26:14

#19 Blocking vs Non Blocking assignment | frequently asked during VLSI JOB INTERVIEW |Very important

36:18

System Design Interview - Top K Problem (Heavy Hitters)

15:08

#21 Why delays are not synthesizsble in verilog or HDL | VLSI interview question

30:12

PROCEDURAL ASSIGNMENT