#20 Inter and intra assignment delay | gate delay,wire delay,inertia and transport delay in verilog
15:08
#21 Why delays are not synthesizsble in verilog or HDL | VLSI interview question
21:47
#17 Delays in verilog | Rise time, fall time,turn off delay explained in details with Testbench
12:10
Inertial and Transport Delays
25:55
#18 Timing control in verilog | Delay based, Event based,Level sensitive timing control with example
18:54
#14 always block for sequential logic || always block in Verilog || explained with codes and ckt.
19:41
#8 Data flow modeling in verilog | explanation with logic circuit and verilog code
24:21
#22 How to write TESTBENCH in verilog || use of $monitor, $display,$Stop,$finish in verilog
26:14