VLSI : synchronous reset vs asynchronous reset active low
6:53
VLSI : clock divider verilog code and clock divider by 2 and frequency divider
8:11
Implementation of MOD-N synchronous counter using IC74191. Explained with example MOD-12 and MOD-8.
13:23
Blocking and Non Blocking Assignments in Verilog | S Vijay Murugan | Learn Thought
12:05
Synchronous Reset and Asynchronous Reset | Synchronous Reset Vs Asynchronous Reset | What is Reset?
8:44
Active low reset | Active high reset | Flop active high reset | Flop active high reset
16:26
Reset active low and high with code and waveform
11:31
[Synthesis/STA] fixing setup and hold timing concepts
5:27