FPGA/SoC Board Bring-Up - DDR3 (Zynq Part 2) - Phil's Lab #97
13:29
FPGA/SoC Board Bring-Up - QSPI (Zynq Part 3) - Phil's Lab #98
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Interfacing FPGAs with DDR Memory - Phil's Lab #115
53:20
What You Need to Know When Routing DDR3 Part 1 of 2
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EEVblog #1247 - DDR Memory PCB Propagation Delay & Layout
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Design of STM32 Development Board with CAN, GPIOs and USB Type-C Interface | Magnetized Labs 02
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Gigabit Ethernet + FPGA/SoC Bring-Up (Zynq Part 4) - Phil's Lab #99
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FPGA/SoC Board Bring-Up Tutorial (Zynq Part 1) - Phil's Lab #96
32:27