26:14

#19 Blocking vs Non Blocking assignment | frequently asked during VLSI JOB INTERVIEW |Very important

15:08

#21 Why delays are not synthesizsble in verilog or HDL | VLSI interview question

21:47

#17 Delays in verilog | Rise time, fall time,turn off delay explained in details with Testbench

25:49

#20 Inter and intra assignment delay | gate delay,wire delay,inertia and transport delay in verilog

24:57

#11 always block in Verilog || procedural block in Verilog explained in details with code

15:25

#1 Why verilog is a popular HDL | properties of verilog Language

8:35:28

Curso Completo de Lógica de Programação com Português Estruturado do Zero ao Avançado

24:21

#22 How to write TESTBENCH in verilog || use of $monitor, $display,$Stop,$finish in verilog