ZYNQ Training - session 03 - axi stream interface
1:10:49
ZYNQ Training - Session 04 - Designing with AXI using Xilinx Vivado
13:46
ZYNQ Training - session 02 - What is an AXI Interconnect?
18:56
The AXI Protocol, AXI MM and AXI Streaming Interfaces [English]
12:11
AXI Stream basics for beginners! A Stream FIFO example in Verilog.
7:04
What is AXI (Part 1)
31:29
Introduction to Direct Memory Access (DMA)
27:49
Using AXI DMA in Vivado
19:52