Performing DRC, LVS and Post-Layout Simulations using Cadence Virtuoso: VLSI Systems Lab Series 3c
18:43
Creating the Layout of an Inverter using Cadence Virtuoso: VLSI Systems Lab Series 3b
24:00
How to extract layout using virtuoso XL (2 input NAND gate example): VLSI Systems Lab Series 4
27:20
Introduction to Cadence Virtuoso: VLSI Systems Lab Series 2
32:00
IC616 Virtuoso Layout demo Part 2 -- Layout of Inverter, DRC, LVS, and PEX
21:57
Introduction to Hierarchical Design using Virtuoso: 2 input AND gate example
9:21
Getting Started with Xilinx Vivado & Nexys A7 FPGA: VLSI System Lab Series 1
8:41
Creating CMOS Layouts and Stick Diagrams: A Step-by-Step Guide
15:10