ILA in a Zynq: View signals in hardware!
43:58
In-System Debugging with Vivado Using ILA Core
10:15
Vivado IP generator tricks: Generating IP, saving to version control, and generating example code!
12:11
AXI Stream basics for beginners! A Stream FIFO example in Verilog.
20:00
Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)
14:51
AXI DMA and Debugging with ILA Part 2: Vitis Design in Polling and Interrupt Modes
8:42
How to Use Sigrok PulseView Software | Logic Analyzer Tutorial
27:49
Using AXI DMA in Vivado
26:04