AMD/Xilinx Versal - Insert AI Engine into your custom PL design and take it to hardware in 15 min
1:00:43
Webinar | How to Use the Versal ACAP NoC
11:48
AMD/Xilinx Versal - Modifying the PL of your AI Engine design
10:31
We fixed an inconsistency in Kotlin (non-local break & continue)
42:39
FPGA Timing Optimization: Optimization Strategies
56:16
FPGAs are (not) Good at Deep Learning [Invited]
56:32
Gas Analysis in Real Time by Mass Spectrometry
27:34
FPGA + PCIe Hardware Accelerator Design Walkthrough (DDR3, M.2, ..) - Phil's Lab #82
34:12