6:45

21.2.2 Data-level Parallelism

1:17:35

4. Assembly Language & Computer Architecture

9:01

19.2.1 Interprocess Communication

6:17

7.2.1 Latency and Throughput

7:10

14.2.7 Direct-mapped Caches

8:42

12.2.2 Activation Records and Stacks

7:32

19.2.2 Semaphores

10:17

16.2.4 Building the MMU