[1/5] UCIe PHY Modeling and Simulation with XMODEL / UCIe Overview and Introduction to XMODEL
28:42
[2/5] UCIe PHY Modeling and Simulation with XMODEL / UCIe Electrical Layer Modeling (Part 1)
1:37:43
Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification
1:00:30
Introduction to UCIe™
11:40
What is an Ethernet PHY?
53:51
How language model post-training is done today
59:18
Introducing the UCIe 2.0 Specification Supporting 3D Packaging and Manageability System Architecture
27:15
Chiplets & UCIe : Overview
1:00:08