VLSI Physical Design: Powerplan
19:04
VLSI Physical Design: Clock Tree Synthesis (CTS)
23:07
Mastering Low-Power CMOS Design in VLSI: Techniques and Best Practices
9:10
VLSI Physical Design: Physical only cells
1:15:09
PNR placement discussion on placement blockages & congestion
12:33
Power Gating and Mother/Daughter cells in VLSI
19:50
DVD - Lecture 6e: Power Planning
8:41
Writing UPF for a given power intent
16:12