VHDL
12:11
Designing Billions of Circuits with Code
28:41
FPGA Design Tutorial (Verilog, Simulation, Implementation) - Phil's Lab #109
22:59
The Dome Paradox: A Loophole in Newton's Laws
10:44
MINI PROJECT(Multiplexer Design with Thread Scheduling and Circular Queue Implementation)
10:01
Algorithms and Data Structures for New Models of Computation
7:08
conceptual classes and relationships / software architecture and design relationships
20:00
Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)
21:59