How the AXI-style ready/valid handshake works
10:14
How to use the 'stable attribute for checking setup and hold times and pulse widths of VHDL signals
10:11
How to create a signal vector in VHDL: std_logic_vector
14:49
RS232 flow control
18:56
The AXI Protocol, AXI MM and AXI Streaming Interfaces [English]
14:22
How the Clock Tells the CPU to "Move Forward"
5:52
The Ready Valid Protocol
19:09
This is the code that sent Apollo 11 to the moon (and it’s awesome)
9:50