Cadence Layout Tutorial
![](https://i.ytimg.com/vi/S-eR3aFfT7c/mqdefault.jpg)
1:02:06
Cadence tutorial - Layout of CMOS NAND gate
![](https://i.ytimg.com/vi/oGfvVkD_3lU/mqdefault.jpg)
2:43:38
PCB Editor Designing PCB Editor 6 layers
![](https://i.ytimg.com/vi/AjKTnIHvuAI/mqdefault.jpg)
44:06
Layout design and post layout simulation in Spectre
![](https://i.ytimg.com/vi/-yP8zRHmeQg/mqdefault.jpg)
36:10
Cadence Schematic Composer Tutorial - Part 2
![](https://i.ytimg.com/vi/YP6oobkUn7E/mqdefault.jpg)
26:14
Layout Basics
![](https://i.ytimg.com/vi/Z5WKIDbthdg/mqdefault.jpg)
19:58
Place and Route with Cadence SOC Encounter (Basics)
![](https://i.ytimg.com/vi/_r67NJWJvus/mqdefault.jpg)
39:34
L10B - Cadence Generic 14nm FinFET Layout and Structure (Part I)
![](https://i.ytimg.com/vi/tK9St35jATA/mqdefault.jpg)
19:41