Cadence IC6.1.6/6.1.7 Virtuoso Tutorial -1 Part 4 (Layout Design and Physical Verification)
25:32
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37:47
Cadence IC6.1.6/6.1.7 Virtuoso Tutorial -1 Part1 (Schematic and symbol Design)
19:41
Cadence Virtuoso:: CMOS Inverter Layout || Part-2.
50:46
Synthesis in Synopsys Design Vision GUI tutorial
23:18
Cadence Virtuoso:: Layout of NAND Gate || Part-2.
21:13
Layout DRC, LVS, PEX and Post Layout Simulation
33:43
Cadence IC6.16/6.17 Virtuoso Tutorial -1 Part 2 (Simulation, Analysis and calculator use)
19:58