Advanced RISC-V Processor Verification Methodology, by Larry Lapides, VP WW Sales, Imperas Software
23:34
Revolutionary Metal I-fuse® OTP in FinFET Tech, by Shine Chung, Chairman, Attopsemi Technology
21:27
IP QA Best Practices, by Siddharth Ravikumar, Technical Product Manager, Solido, Siemens EDA
2:07:56
Introduction to the 5 Levels of RISC-V Processor Verification
1:03:03
NVIDIA CEO Jensen Huang's Vision for Your Future
27:31
PCI Express 6.0 – Physical Layer Characterization of a Low Latency PAM4 Link at 64GT/s, David Bouse
29:49
Journey to the Best Performance-per-Watt at 3nm and Below, by James Chuang, Product Manager Synopsys
1:49:55
How To Speak Fluently In English About Almost Anything
22:03